The present invention relates in general to input/output (I/O) interface architectures in integrated circuits, and in particular to memory interface phase-shift circuitry that supports multiple frequency ranges.
Typical I/O architectures transmit a single data bit on each positive edge of a strobe signal and are limited to the speed of the strobe signal. To address the problem of data bandwidth bottleneck between integrated circuits, high speed interface mechanisms have been developed to increase the speed of data transfer and data throughput. In a multiple data rate (MDR) interface scheme, two or more data bits are transferred during each clock period of the strobe signal. For example, in a double data rate (DDR) interface scheme, data can be captured on both a rising edge and a falling edge of the clock to achieve twice the throughput of data. Multiple data rate technologies have thus accelerated the I/O performance of integrated circuits for a wide array of applications from computers to communication systems. For example, the MDR technologies are being employed in today's memory interfaces including interfaces for the double data rate synchronous dynamic random access memory (DDR SDRAM), fast cycle random access memory (FCRAM), reduced latency dynamic random access memory (DRAM I or RLDRAM I or RLDRAM II), and quadruple data rate static random access memory (QDR) as well as other high-speed interface standards.
Programmable logic devices (PLD) have been used to implement memory interface controllers for memory interfaces such as the DDR, QDR, or RLDRAM interfaces. The flexibility of programmable logic in customizing features of the memory interface controller, in addition to the ability to modify the design on-the-fly to meet difficult memory interface timing requirements, are two of the primary advantages of using programmable logic in these applications. To better meet memory timing requirements, dedicated hardware has been added to the PLDs that interface with high-speed memories.
For example, in a basic DDR implementation, a strobe signal (DQS) controls the timing of the transfer of a group of I/O data (also referred to as DQ signals). As mentioned before, for DDR memories, the DQ data are sent on the rising and falling edges of the strobe, as opposed to only once per clock cycle. During a read operation, read data DQ is captured at the PLD side on both rising and falling edges of the read strobe DQS, thus, two bits of data are captured in every cycle. As shown in FIG. 1, the read strobe DQS usually arrives from the memory edge-aligned with the read data DQ. To ensure that valid data is captured by the PLD, the DQS signal needs to be phase-shifted so that the DQS edges are aligned with the centers of data sampling windows associated with the DQ signals. So, PLDs interfacing with DDR memories often include dedicated phase-shifting circuitry to produce the phase-shifted DQS signals.
Typical phase shift techniques that use, for example, delay chains, are highly susceptible to process, voltage, and temperature (PVT) variations. A delay-locked-loop (DLL) circuit can be used to account for these PVT variations and to provide a setting to the delay chain that dictates the number of delay increments to be taken by the delay chain in order to produce the desired amount of phase shift, such as a 90 degree phase shift or a 72 degree phase shift. The number of available settings and the size of the delay increment are associated with the range of memory frequencies supported by the PLD. As the frequency range supported by the PLD becomes larger, such as from a range of 133 MHz to 200 MHz to a range of 100 to 300 MHz, greater demands are placed on the PLD, and in particular on the phase-shift circuitry.